- ChrisP –
Understanding Hardware Device Resources Part One – IRQ’s
Anyone who has ever tried to install a legacy (non plug-and-play) device has learned that device configuration can be a world of confusion for the novice. Fortunately, the entire concept of device configuration can be simplified through the understanding of a few basic terms and concepts.
When discussing device configuration, we typically hear about three basic types of hardware resources: Interrupt Request (IRQ) Line Assignments, Direct Memory Access (DMA) Assignments, and memory locations known as Input/Output (I/O) Addresses. In this series of three articles, I will discuss each of these terms with the intent of clarifying device configuration and resource conflict resolution. This discussion is based upon and applies primarily to current-design IBM-compatible systems operating under Microsoft Windows 98, although the other 32-bit versions of Windows are similar.
Device resource conflicts occur whenever two or more hardware devices attempt to utilize the same resource. Normally, a conflict will simply stop one or more of the involved devices from operating properly. Often, this will be nothing more than an inconvenient nuisance. Sometimes however, the result is far more serious, to the point of not allowing Windows to load properly. A solid understanding of device resources and their assignments can assist the user in avoiding resource conflicts.
Interrupt Request (IRQ) Line Assignments
The Interrupt Request Lines, also known as hardware interrupts, are dedicated signal lines or circuits between the system CPU and hardware devices. These signal lines are used for the purpose of notifying the CPU that the assigned device needs processor attention and vice versa. The simplest way to understand IRQ’s is to consider the IRQ as a doorbell… when a device requires CPU attention, it places a signal on its assigned IRQ line. The CPU senses this signal and responds by stopping it’s current operation and shifting its attention to the “interrupting” device.
In this modern era of high-speed computers, we like to think that our PC’s are whizzes at doing multiple jobs simultaneously. Hold on to your hats for the reality of it, folks – for all practical purposes, even the fastest CPU in a PC today is only capable of doing one thing at a time! It only seems like the CPU is doing multiple jobs, due to the fact that the CPU is capable of switching between tasks tens of thousands of times every second. To mere mortals, the apparent effect is that of a CPU doing all kinds of things at the same time. OK, so what does any of this have to do with IRQ’s? As a kind of answer, ask yourself a question – “What happens when I try to talk to someone who is too busy to listen?” The IRQ’s are the chosen method of making the (too busy) CPU listen to the other devices in the PC. When the CPU receives an IRQ signal, it must stop what it is doing and devote its attention to the interrupting device. These hardware interrupts are known as maskable interrupts, meaning that the processor can temporarily mask or ignore the interrupt request long enough to complete its current task. There is also a Non-Maskable Interrupt or NMI – an interrupt that cannot be ignored even temporarily – but we’re not going to worry about that for this discussion, as it is in no way user-configurable.
Let’s look at a basic rundown of what is behind the whole hardware interrupt scheme. Consider the system keyboard. The keyboard controller on a typical system is a fairly limited device, with no real storage capability (memory) to speak of, and the CPU is responsible for moving the keystroke to the keyboard buffer. Each time the user presses a key, the generated keystroke signal must be passed off to the CPU immediately, because the next incoming keystroke will replace or overwrite the previous one if that one hasn’t been stored yet. So what would happen to the incoming keystrokes if the CPU is busy doing something else and so is unable to handle them? The obvious answer is that they would be lost. To prevent this from occurring, the engineers have given the keyboard system the ability to demand processor attention. The keyboard controller, immediately upon receipt of an incoming keystroke, activates its assigned hardware interrupt line (IRQ1). The Intel 8259A IRQ controller chip accepts this interrupt request and passes it on to the processor’s interrupt line. The processor in turn shifts its focus to the incoming keystrokes and handles them in the prescribed manner. There is a pre-determined routine to be followed by the system for each of the PC’s interrupt lines.
Two things of note should be remembered when reading this. One is that there is really a lot more involved than just the few simple steps that I’ve described here; the process was simplified for this discussion by stripping it down to just its pertinent factors. The other is that this all occurs at incredibly high rates of speed – thousands of times per second. Consider the concept of a 200 MHz CPU that can process 20 million instructions between each keystroke of 120 word-per-minute typist, based on an average of five characters per word.
OK, so now that we have seen the basics of interrupt operation, we should look at some more detail about their deployment in the system. The original PC and XT systems used 8-bit ISA expansion slots, and had eight hardware interrupt lines. Figure 1 below shows the default IRQ assignments for the XT-class machines.
|IRQ||Function or Assignment||On Bus?|
|3||Serial Port 1 (COM2:)||Yes|
|4||Serial Port 0 (COM1:)||Yes|
|5||Hard Disk Drive Controller||Yes|
|6||Floppy Disk Drive Controller||Yes|
|7||Parallel Port 0 (LPT1:)||Yes|
Note that not all of the interrupt lines were made available to the expansion bus. Only those IRQ’s that are available to the bus can be used by expansion devices installed to the bus. In other words, no user-installed expansion card could be assigned either IRQ0 or IRQ1, as there were no connections for those IRQ’s assigned in the ISA 8-bit expansion slot.
In earlier (pre-AT) systems, IRQ2 was reserved for certain video adapter types. With the introduction of the 16-bit ISA bus and the VGA standard, that reservation was pretty much no longer needed, but there was a need for additional IRQ lines. In keeping with the desire for backward compatibility, the engineers devised a scheme that would allow the additional IRQ lines to have processor access without changing the basic structure already in place. The result was the cascaded IRQ’s numbered 8 through 15. These newly created IRQ’s are connected to the CPU through the basically unused IRQ2 connection.
|IRQ||Function or Assignment||On Bus?||Bits?|
|2||Second IRQ Controller||No||–|
|9||Available (shows as IRQ2 on 8-bit cards)||Yes||8|
|12||Motherboard (PS/2) Mouse Port||Yes||16|
|14||Hard Disk Drive Controller||Yes||16|
|3||Serial Port 1 (COM2:)||Yes||8|
|4||Serial Port 0 (COM1:)||Yes||8|
|5||Parallel Port 1 (LPT2:)||Yes||8|
|6||Floppy Disk Drive Controller||Yes||8|
|7||Parallel Port 0 (LPT1:)||Yes||8|
The existing IRQ2 line was removed from the 8-bit ISA slot and made available as a motherboard connection. A second Intel 8259A chip was added as a controller for the new IRQ’s. Its output line connects to the IRQ2 line on the primary 8259A controller as an input. The line designated as IRQ9 on the new controller was then connected to the former IRQ2 connector on the 8-bit ISA slot. Most of the remaining IRQ lines of the secondary 8259A were then brought out to connections on the new 16-bit extension portion of the ISA expansion slot. Thus, we now have fifteen unique interrupt lines communicating to the CPU via the path that previously supported 8 interrupt lines. Figure 2 shows the default IRQ assignments for the AT-class machines.
There is a certain amount of prioritization that occurs due to IRQ lines, but the effect of this prioritization is not really noticeable on today’s high-speed computers. In a nutshell, the CPU responds to IRQ signals in their numerical order. In other words, if two devices apply an IRQ signal simultaneously, the device with the lower IRQ number gets the CPU’s attention first. However, there is a catch to this scheme, which is hinted at in Figure 2. All of the interrupts handled by the second IRQ controller are prioritized after IRQ1 (the keyboard), but before IRQ3 (COM2:). This is due to the fact that they are connected to the first IRQ controller in place of the original IRQ2, and the entire second controller has therefore inherited the old IRQ2 priority position.
Your PC has a limited number of IRQ’s available – effectively fifteen on a modern system. Of these fifteen existing IRQ’s, several are permanently assigned to specific mainboard devices and cannot be used for other purposes. The following chart (Figure 3) shows the typical IRQ assignments in use today. Note that some of the assignments are flexible (indicated by *), while others cannot be changed.
|IRQ Line||Typical Device||Comments and Probable User Assignments|
|0||System Timer||Hard-configured; unavailable for user assignment|
|1||Keyboard Controller||Hard-configured; unavailable for user assignment|
|2||Cascade from IRQ9||(see IRQ9)|
|5||(available)*||Modem, sound card, second parallel port|
|6||Floppy Controller||Normally not available for user assignment|
|8||Real Time Clock||Hard-configured; unavailable for user assignment|
|9||(available)*||Modem, network adapter, sound card|
|10||(available)*||SCSI adapter, sound card, USB controller|
|11||(available)*||network adapter, SCSI adapter, video adapter|
|12||PS/2 Mouse*||Available only if using non-PS/2 pointing device|
|13||NPU||Normally not available for user assignment|
|14||Primary IDE||Normally not available for user assignment|
|15||Secondary IDE||Normally not available for user assignment|
As can be seen in the chart, there are basically four IRQ’s to choose from when installing additional devices into a standard PC. That’s not a whole lot to work with! Now consider all of the devices that are found in most new PC’s today. What happens when you try to add a modem, a sound card, a network adapter, a SCSI card, and a second printer port? A long-standing problem has been that two devices cannot share a single IRQ and have both devices work properly at the same time. We simply have more devices requiring IRQ’s than we have available IRQ lines to assign! The engineers solved this dilemma with the introduction of the PCI (Peripheral Component Interconnect) bus.
For the first time, the PCI bus allowed for managed sharing of hardware interrupts. We can now have multiple PCI devices assigned to the same physical IRQ line, because the PCI chipset manages communication between the PCI devices and the processor. For this reason, it is perfectly normal today to see two or three devices assigned to the same IRQ. In this case, you will also see entries such as IRQ Holder for PCI Steering.